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Fix wrong date in changelog

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Robbert van der Helm
2025-09-07 23:34:16 +02:00
parent 51a5db17f6
commit 28b149ec4d
2 changed files with 20 additions and 32 deletions
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2
CHANGELOG.md
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@@ -10,7 +10,7 @@ Since there is no stable release yet, the changes are organized per day in
reverse chronological order. The main purpose of this document in its current reverse chronological order. The main purpose of this document in its current
state is to list breaking changes. state is to list breaking changes.
## [2024-02-23] ## [2025-02-23]
### Breaking changes ### Breaking changes

50
src/wrapper/util.rs
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@@ -9,6 +9,15 @@ pub(crate) mod buffer_management;
#[cfg(debug_assertions)] #[cfg(debug_assertions)]
pub(crate) mod context_checks; pub(crate) mod context_checks;
/// The bit that controls flush-to-zero behavior for denormals in 32 and 64-bit floating point
/// numbers on x86 family architectures. Rust 1.75 deprecated the built in functions for controlling
/// these registers. As listed in section 10.2.3.3 (Flush-To-Zero), bit 15 of the MXCSR register
/// controls the FTZ behavior.
///
/// <https://cdrdv2-public.intel.com/843823/252046-sdm-change-document-1.pdf>
#[cfg(target_feature = "sse")]
const SSE_FTZ_BIT: u32 = 1 << 15;
/// The bit that controls flush-to-zero behavior for denormals in 32 and 64-bit floating point /// The bit that controls flush-to-zero behavior for denormals in 32 and 64-bit floating point
/// numbers on AArch64. /// numbers on AArch64.
/// ///
@@ -207,25 +216,16 @@ impl ScopedFtz {
{ {
#[cfg(target_feature = "sse")] #[cfg(target_feature = "sse")]
{ {
const X86_FTZ_BIT: u32 = 1 << 15; // Rust 1.75 deprecated `_mm_setcsr()` and `_MM_SET_FLUSH_ZERO_MODE()`, so this now
// requires inline assembly. See sections 10.2.3 (MXCSR Control and Status Register)
// and 10.2.3.3 (Flush-To-Zero) from this document for more details:
//
// <https://cdrdv2-public.intel.com/843823/252046-sdm-change-document-1.pdf>
let mut mxcsr: u32 = 0; let mut mxcsr: u32 = 0;
unsafe { unsafe { std::arch::asm!("stmxcsr [{}]", in(reg) &mut mxcsr) };
std::arch::asm!( let should_disable_again = mxcsr & SSE_FTZ_BIT == 0;
"stmxcsr [{p}]",
p = in(reg) &mut mxcsr,
options(nostack, preserves_flags),
);
}
let should_disable_again = (mxcsr & X86_FTZ_BIT) == 0;
if should_disable_again { if should_disable_again {
let new_mxcsr = mxcsr | X86_FTZ_BIT; unsafe { std::arch::asm!("ldmxcsr [{}]", in(reg) &(mxcsr | SSE_FTZ_BIT)) };
unsafe {
std::arch::asm!(
"ldmxcsr [{p}]",
p = in(reg) &new_mxcsr,
options(nostack, preserves_flags),
);
}
} }
return Self { return Self {
@@ -268,21 +268,9 @@ impl Drop for ScopedFtz {
if self.should_disable_again { if self.should_disable_again {
#[cfg(target_feature = "sse")] #[cfg(target_feature = "sse")]
{ {
const X86_FTZ_BIT: u32 = 1 << 15;
let mut mxcsr: u32 = 0; let mut mxcsr: u32 = 0;
unsafe { unsafe { std::arch::asm!("stmxcsr [{}]", in(reg) &mut mxcsr) };
std::arch::asm!( unsafe { std::arch::asm!("ldmxcsr [{}]", in(reg) &(mxcsr & !SSE_FTZ_BIT)) };
"stmxcsr [{p}]",
p = in(reg) &mut mxcsr,
options(nostack, preserves_flags),
);
let new_mxcsr = mxcsr & !X86_FTZ_BIT;
std::arch::asm!(
"ldmxcsr [{p}]",
p = in(reg) &new_mxcsr,
options(nostack, preserves_flags),
);
}
} }
#[cfg(target_arch = "aarch64")] #[cfg(target_arch = "aarch64")]